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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7755* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 energy metering ic with pulse output functional block diagram multiplier ac/ dc clkout v1p v1n g0 v2p g1 av dd dv dd hpf clkin ref in/out f1 f2 cf revp scf s0 s1 reset agnd dgnd phase correction 4k ... 110101 ... signal processing block adc pga x1, x2, x8, x16 power supply monitor adc v2n ad7755 ... 11011001 ... lpf 2.5v reference digital-to-frequency converter features high accuracy, supports 50 hz/60 hz iec 521/1036 less than 0.1% error over a dynamic range of 500 to 1 the ad7755 supplies average real power on the frequency outputs f1 and f2 the high frequency output cf is intended for calibration and supplies instantaneous real power the logic output revp can be used to indicate a potential miswiring or negative power direct drive for electromechanical counters and two phase stepper motors (f1 and f2) a pga in the current channel allows the use of small values of shunt and burden resistance proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time on-chip power supply monitoring on-chip creep protection (no load threshold) on-chip reference 2.5 v 8% (30 ppm/ c typical) with external overdrive capability single 5 v supply, low power (15 w typical) low cost cmos process general description the ad7755 is a high accuracy electrical energy measurement ic. the part specifications surpass the accuracy requirements as quoted in the iec1036 standard. the only analog circuitry used in the ad7755 is in the adcs and reference circuit. all other signal processing (e.g., multipli- cation and filtering) is carried out in the digital domain. this approach provides superior stability and accuracy over extremes in environmental conditions and over time. the ad7755 supplies average real power information on the low frequency outputs f1 and f2. these logic outputs may be used to directly drive an electromechanical counter or interface to an mcu. the cf logic output gives instantan eous real power information. this output is intended to be used for calibration purposes, or interfacing to an mcu. the ad7755 includes a power supply monitoring circuit on the av dd supply pin. the ad7755 will remain in a reset condition until the supply voltage on av dd reaches 4 v. if the supply falls below 4 v, the ad7755 will also be reset and no pulses will be issued on f1, f2 and cf. internal phase matching circuitry ensures that the voltage and current channels are phase matched whether the hpf in chan- nel 1 is on or off. an internal no-load threshold ensures that the ad7755 does not exhibit any creep when there is no load. the ad7755 is available in 24-lead dip and ssop packages. *u.s. patents 5,745,323, 5,760,617, 5,862,069, 5,872,469.
rev. 0 ? ad7755?pecifications (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.58 mhz, t min to t max = ?0 c to +85 c) parameter a version b version units test conditions/comments accuracy 1, 2 measurement error 1 on channel 1 channel 2 with full-scale signal ( 660 mv), +25 c gain = 1 0.1 0.1 % reading typ over a dynamic range 500 to 1 gain = 2 0.1 0.1 % reading typ over a dynamic range 500 to 1 gain = 8 0.1 0.1 % reading typ over a dynamic range 500 to 1 gain = 16 0.1 0.1 % reading typ over a dynamic range 500 to 1 phase error 1 between channels line frequency = 45 hz to 65 hz v1 phase lead 37 (pf = 0.8 capacitive) 0.1 0.1 degrees( ) max ac/ dc = 0 and ac/ dc = 1 v1 phase lag 60 (pf = 0.5 inductive) 0.1 0.1 degrees( ) max ac/ dc = 0 and ac/ dc = 1 ac power supply rejection 1 ac/ dc = 1, s0 = s1 = 1, g0 = g1 = 0 output frequency variation (cf) 0.01 0.01 % reading typ v1 = 100 mv rms, v2 = 100 mv rms, @ 50 hz ripple on av dd of 200 mv rms @ 100 hz dc power supply rejection 1 ac/ dc = 1, s0 = s1 = 1, g0 = g1 = 0 output frequency variation (cf) 0.01 0.01 % reading typ v1 = 100 mv rms, v2 = 100 mv rms, av dd = av dd = 5 v 250 mv analog inputs see analog inputs section maximum signal levels 1 1 v max v1p, v1n, v2n and v2p to agnd input impedance (dc) 400 400 k ? min clkin = 3.58 mhz bandwidth (C3 db) 14 14 khz typ clkin/256, clkin = 3.58 mhz adc offset error 1, 2 15 15 mv max see terminology and gain error 1 4 4 % ideal typ external 2.5 v reference, gain = 1 v1 = 470 mv dc, v2 = 660 mv dc gain error match 1 0.2 0.2 % ideal typ external 2.5 v reference reference input ref in/out input voltage range 2.7 2.7 v max 2.5 v + 8% 2.3 2.3 v min 2.5 v C 8% input impedance 3.7 3.7 k ? min input capacitance 10 10 pf max on-chip reference nominal 2.5 v reference error 200 200 mv max temperature coefficient 30 30 ppm/ c typ 60 ppm/ c max clkin note all specifications for clkin of 3.58 mhz input clock frequency 4 4 mhz max 1 1 mhz min logic inputs 3 scf, s0, s1, ac/ dc , reset , g0 and g1 input high voltage, v inh 2.4 2.4 v min dv dd = 5 v 5% input low voltage, v inl 0.8 0.8 v max dv dd = 5 v 5% input current, i in 3 3 a max typically 10 na, v in = 0 v to dv dd input capacitance, c in 10 10 pf max logic outputs 3 f1 and f2 output high voltage, v oh i source = 10 ma 4.5 4.5 v min dv dd = 5 v output low voltage, v ol i sink = 10 ma 0.5 0.5 v max dv dd = 5 v cf and revp output high voltage, v oh i source = 5 ma 4 4 v min dv dd = 5 v output low voltage, v ol i sink = 5 ma 0.5 0.5 v max dv dd = 5 v
rev. 0 3 ad7755 parameter a version b version units test conditions/comments power supply for specified performance av dd 4.75 4.75 v min 5 v C 5% 5.25 5.25 v max 5 v + 5% dv dd 4.75 4.75 v min 5 v C 5% 5.25 5.25 v max 5 v + 5% ai dd 3 3 ma max typically 2 ma di dd 2.5 2.5 ma max typically 1.5 ma notes 1 see terminology section for explanation of specifications. 2 see plots in typical performance graphs. 3 sample tested during initial release and after any redesign or process change that may affect this parameter. specifications subject to change without notice. timing characteristics 1, 2 parameter a, b versions units test conditions/comments t 1 3 275 ms f1 and f2 pulsewidth (logic low) t 2 see table iii sec output pulse period. see transfer function section t 3 1/2 t 2 sec time between f1 falling edge and f2 falling edge t 4 3, 4 90 ms cf pulsewidth (logic high) t 5 see table iv sec cf pulse period. see transfer function section t 6 clkin/4 sec minimum time between f1 and f2 pulse notes 1 sample tested during initial release and after any redesign or process change that may affect this parameter. 2 see figure 1. 3 the pulsewidths of f1, f2 and cf are not fixed for higher output frequencies. see frequency outputs section. 4 the cf pulse is always 1 s in the high frequency mode. see frequency outputs section and table iv. specifications subject to change without notice. ordering guide model package description package options AD7755AN plastic dip n-24 ad7755ars shrink small outline package rs-24 ad7755brs shrink small outline package rs-24 (av dd = dv dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, clkin = 3.58 mhz, t min to t max = ?0 c to +85 c) . t 2 . t 3 t 4 . t 5 . t 6 t 1 f1 f2 cf figure 1. timing diagram for frequency outputs
rev. 0 ad7755 4 absolute maximum ratings* (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dv dd to av dd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v analog input voltage to agnd v1p, v1n, v2p and v2n . . . . . . . . . . . . . . . C6 v to +6 v reference input voltage to agnd . . C0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . C0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . C0.3 v to dv dd + 0.3 v operating temperature range industrial (a, b versions) . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . +150 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7755 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device 24-lead plastic dip, power dissipation . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . 105 c/w lead temperature, (soldering 10 sec) . . . . . . . . . . +260 c 24-lead ssop, power dissipation . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . 112 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminology measurement error the error associated with the energy measurement made by the ad7755 is defined by the following formula: percentage error true energy = energy registered by the ad7755 ? true energy 100% phase error between channels the hpf (high pass filter) in channel 1 has a phase lead response. to offset this phase response and equalize the phase response between channels, a phase correction network is also placed in channel 1. the phase correction network matches the phase to within 0.1 over a range of 45 hz to 65 hz and 0.2 over a range 40 hz to 1 khz. see figures 22 and 23. power supply rejection this quantifies the ad7755 measurement error as a percentage of reading when the power supplies are varied. for the ac psr measurement a reading at nominal supplies (5 v) is taken. a 200 mv rms/100 hz signal is then introduced onto the supplies and a second reading obtained under the same input signal levels. any error introduced is expressed as a per- centage of readingsee measurement error definition. for the dc psr measurement a reading at nominal supplies (5 v) is taken. the supplies are then varied 5% and a second reading is obtained with the same input signal levels. any error introduced is again expressed as a percentage of reading. adc offset error this refers to the dc offset associated with the analog inputs to the adcs. it means that with the analog inputs connected to agnd the adcs still see an analog input signal of 1 mv to 10 mv, depending on gain setting. however, when the hpf is switched on, the offset is removed from the current channel and the power calculation is not affected by this offset. gain error the gain error of the ad7755 is defined as the difference be- tween the measured output frequency (minus the offset) and the ideal output frequency. it is measured with a gain of 1 in chan- nel v1. the difference is expressed as a percentage of the ideal frequency. the ideal frequency is obtained from the ad7755 transfer functionsee transfer function section. gain error match the gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 and a gain of 2, 8, or 16. it is expressed as a percentage of the out- put frequency obtained under a gain of 1. this gives the gain error observed when the gain selection is changed from 1 to 2, 8 or 16.
rev. 0 ad7755 5 pin function descriptions pin no. mnemonic description 1dv dd digital power supply. this pin provides the supply voltage for the digital circuitry in the ad7755. the supply voltage should be maintained at 5 v 5% for specified operation. this pin should be decoupled with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 2 ac/ dc high pass filter select. this logic input is used to enable the hpf in channel 1 (the current channel). a logic one on this pin enables the hpf. the associated phase response of this filter has been inter- nally compensated over a frequency range of 45 hz to 1 khz. the hpf filter should be enabled in power metering applications. 3av dd analog power supply. this pin provides the supply voltage for the analog circuitry in the ad7755. the supply should be maintained at 5 v 5% for specified operation. every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. this pin should be decoupled to agnd with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 4, 19 nc no connect. 5, 6 v1p, v1n analog inputs for channel 1. these inputs are fully differential voltage inputs with a maximum signal level of 470 mv with respect to pin v1n for specified operation. channel 1 also has a pga and the gain selections are outlined in table i. the maximum signal level at this pin is 1 v with respect to agnd. both inputs have internal esd protection circuitry and in addition an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 7, 8 v2n, v2p negative and positive inputs for channel 2 (voltage channel). these inputs provide a fully differential input pair. the maximum differential input voltage is 660 mv for specified operation. the maximum signal level at these pins is 1 v with respect to agnd. both inputs have internal esd protection circuitry and an overvoltage of 6 v can also be sustained on these inputs without risk of permanent damage. 9 reset reset pin for the ad7755. a logic low on this pin will hold the adcs and digital circuitry in a reset condition. bringing this pin logic low will clear the ad7755 internal registers. 10 ref in/out this pin provides access to the on-chip voltage reference. the on-chip reference has a nominal value of 2.5 v 8% and a typical temperature coefficient of 30 ppm/ c. an external reference source may also be connected at this pin. in either case this pin should be decoupled to agnd with a 10 f tantalum capacitor and 100 nf ceramic capacitor. 11 agnd this provides the ground reference for the analog circuitry in the ad7755, i.e., adcs and reference. this pin should be tied to the analog ground plane of the pcb. the analog ground plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. for good noise suppression the analog ground plane should only connected to the digital ground plane at one point. a star ground configuration will help to keep noisy digital currents away from the analog circuits. 12 scf select calibration frequency. this logic input is used to select the frequency on the calibration output cf. table iv shows how the calibration frequencies are selected. 13, 14 s1, s0 these logic inputs are used to select one of four possible frequencies for the digital-to-frequency con- version. this offers the designer greater flexibility when designing the energy meter. see selecting a frequency for an energy meter application section. 15, 16 g1, g0 these logic inputs are used to select one of four possible gains for channel 1, i.e., v1. the possible gains are 1, 2, 8 and 16. see analog input section. 17 clkin an external clock can be provided at this logic input. alternatively a crystal can be connected across clkin and clkout to provide a clock source for the ad7755. the clock frequency for specified operation is 3.579545 mhz. crystal load of 33 pf ceramic capacitors should be used with the gate oscillator circuit. 18 clkout a crystal can be connected across this pin and clkin as described above to provide a clock source for the ad7755. the clkout pin can drive one cmos load when an external clock is supplied at clkin. 20 revp this logic output will go logic high when negative power is detected, i.e., when the phase angle be- tween the voltage and current signals is greater that 90 . this output is not latched and will be reset when positive power is once again detected. the output will go high or low at the same time as a pulse is issued on cf.
rev. 0 ad7755 6 pin no. mnemonic description 21 dgnd this provides the ground reference for the digital circuitry in the ad7755, i.e., multiplier, filters and digital-to-frequency converter. this pin should be tied to the analog ground plane of the pcb. the digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and digital), mcus and indicator leds. for good noise suppression the analog ground plane should only be connected to the digital ground plane at one point only, e.g., a star ground. 22 cf calibration frequency logic output. the cf logic output gives instantaneous real power informa- tion. this output is intended to be used for calibration purposes. also see scf pin description. 23, 24 f2, f1 low frequency logic outputs. f1 and f2 supply average real power information. the logic outputs can be used to directly drive electromechanical counters and two phase stepper motors. see transfer function section. pin configuration dip and ssop packages top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad7755 nc = no connect dv dd ac/ dc av dd nc f1 v1p v1n v2n v2p reset ref in/out agnd scf f2 cf dgnd revp nc clkout clkin g0 g1 s0 s1
rev. 0 ad7755 7 amps 0.5 0.01 0.1 % error 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 1 10 100 +25 c +85 c ?0 c pf = 1 gain = 1 on-chip reference figure 2. error as a % of reading (gain = 1) amps 0.5 0.01 0.1 % error 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 1 10 100 +25 c +85 c 40 c pf = 1 gain = 2 on-chip reference figure 3. error as a % of reading (gain = 2) amps 0.4 0.01 0.1 % error 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 1 10 100 +25 c +85 c 40 c pf = 1 gain = 8 on-chip reference figure 4. error as a % of reading (gain = 8) typical performance characteristics amps 0.5 0.01 0.1 % error 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 1 10 100 +25 c +85 c 40 c pf = 1 gain = 16 on-chip reference figure 5. error as a % of reading (gain = 16) amps 0.6 0.01 0.1 % error 0.4 0.2 0.0 0.2 0.4 0.6 1 10 100 40 c pf = 0.5 +25 c pf = 1 +25 c pf = 0.5 +85 c pf = 0.5 pf = 0.5 gain = 1 on-chip reference figure 6. error as a % of reading (gain = 1) amps 0.6 0.01 0.1 % error 0.4 0.2 0.0 0.2 0.4 0.6 1 10 100 40 c pf = 0.5 +25 c pf = 1 +25 c pf = 0.5 +85 c pf = 0.5 pf = 0.5 gain = 2 on-chip reference figure 7. error as a % of reading (gain = 2)
rev. 0 ad7755 8 amps 0.01 0.1 % error 0.0 1 10 100 40 c pf = 0.5 +25 c pf = 1 +25 c pf = 0.5 +85 c pf = 0.5 0.2 0.4 0.6 0.8 0.8 0.6 0.4 0.2 pf = 0.5 gain = 8 on-chip reference figure 8. error as a % of reading (gain = 8) amps 0.01 0.1 % error 0.8 0.6 0.2 0.4 0.0 0.2 0.4 1 10 100 40 c pf = 0.5 1.0 +25 c pf = 1 +25 c pf = 0.5 +85 c pf = 0.5 pf = 0.5 gain = 16 on-chip reference figure 9. error as a % of reading (gain = 16) amps 0.4 0.01 0.1 % error 0.2 0.1 0.0 1 10 100 40 c pf = 1 gain = 2 external reference +25 c +85 c 0.3 0.4 0.2 0.1 0.3 figure 10. error as a % of reading over temperature with an external reference (gain = 2) amps 0.01 0.1 % error 0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 1 10 100 +25 c +85 c 40 c pf = 1 gain = 16 external reference figure 11. error as a % of reading over temperature with an external reference (gain = 16) frequency hz % error 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 45 50 55 60 65 70 75 pf = 1 pf = 0.5 figure 12. error as a % of reading over frequency avdd ac/ dc avdd nc v1p v1n ref in/out 33nf 1k 100nf 33nf 1k v2n 33nf 33nf v2p 100nf 10 f 1k 1k 1m 10 f 100nf 10 f v dd reset agnd dgnd f1 f2 cf revp nc clkout clkin g0 g1 s0 s1 scf y1 3.58mhz 10nf 10nf 10nf 33pf 33pf 500 1.5m 10m 40a to 40ma 220v gain select u3 ps2501-1 k7 k8 u1 ad7755 10k v dd v dd nc = no connect figure 13. test circuit for performance curves
rev. 0 ad7755 9 frequency hz 15 phase degrees 2 0 4 6 8 10 12 14 16 9 33 915 gain = 1 temperature = +25 c distribution characteristics number points: 101 minimum: 9.78871 maximum: 7.2939 mean: 1.73203 std. dev: 3.61157 figure 14. channel 1 offset distribution (gain = 1) frequency hz 15 phase degrees 2 0 4 6 8 12 14 16 18 9 33 915 gain = 2 temperature = +25 c distribution characteristics number points: 101 minimum: 5.61779 maximum: 6.40821 mean: 0.01746 std. dev: 2.35129 10 figure 15. channel 1 offset distribution (gain = 2) frequency hz 15 phase degrees 5 0 10 15 20 25 30 9 33 915 gain = 8 temperature = +25 c distribution characteristics number points: 101 minimum: 2.48959 maximum: 5.81126 mean: 1.26847 std. dev: 1.57404 figure 16. channel 1 offset distribution (gain = 8) frequency hz 15 phase degrees 10 0 15 20 25 30 35 9 33 915 gain = 16 temperature = +25 c distribution characteristics number points: 101 minimum: 1.96823 maximum: 5.71177 mean: 1.48279 std. dev: 1.47802 5 figure 17. channel 1 offset distribution (gain = 16)
rev. 0 ad7755 10 theory of operation the two adcs digitize the voltage signals from the current and voltage transducers. these adcs are 16-bit second order sigma-delta with an oversampling rate of 900 khz. this analog input structure greatly simplifies transducer interfacing by providing a wide dynamic range for direct connection to the transducer and also simplifying the antialiasing filter design. a programmable gain stage in the current channel further facili- tates easy transducer interfacing. a high pass filter in the current channel removes any dc component from the current signal. this eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signalssee hpf and offset effects section. the real power calculation is derived from the instantaneous power signal. the instantaneous power signal is generated by a direct multiplication of the current and voltage signals. in order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered. figure 18 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. this scheme correctly calculates real power for nonsinusoidal current and voltage waveforms at all power factors. all signal processing is carried out in the digital domain for superior stability over temperature and time. lpf digital-to- frequency f1 f2 ch1 instantaneous real power signal multiplier pga ch2 adc instantaneous power signal p(t) v i 2 v i v i 2 p(t) = i(t) v(t) where: v(t) = v cos( t) i(t) = i cos( t) p(t) = v i 2 { 1+cos (2 t)} adc time hpf digital-to- frequency cf figure 18. signal processing block diagram the low frequency output of the ad7755 is generated by accu- mulating this real power information. this low frequency inher- ently means a long accumulation time between output pulses. the output frequency is therefore proportional to the average real power. this average real power information can, in turn, be accumulated (e.g., by a counter) to generate real energy infor- mation. because of its high output frequency and hence shorter integration time, the cf output is proportional to the instanta- neous real power. this is useful for system calibration purposes that would take place under steady load conditions. power factor considerations the method used to extract the real power information from the instantaneous power signal (i.e., by low-pass filtering) is still valid even when the voltage and current signals are not in phase. figure 19 displays the unity power factor condition and a dpf (displacement power factor) = 0.5, i.e., current signal lagging the voltage by 60 . if we assume the voltage and current wave- forms are sinusoidal, the real power component of the instanta- neous power signal (i.e., the dc term) is given by vi ? ? ? ? ? ? 2 cos (60 ). this is the correct real power calculation. instantaneous real power signal instantaneous power signal v i 2 cos(60 ) v i 2 instantaneous power signal instantaneous real power signal 60 current current voltage 0v 0v voltage figure 19. dc component of instantaneous power signal conveys real power information pf < 1 nonsinusoidal voltage and current the real power calculation method also holds true for nonsinu- soidal current and voltage waveforms. all voltage and current waveforms in practical applications will have some harmonic content. using the fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their har- monic content. vt v vh h t h o h ( ) sin( ) =+ + 2 0 ? (1) where: v ( t ) is the instantaneous voltage v o is the average value vh is the rms value of voltage harmonic h and h is the phase angle of the voltage harmonic. it i ih h t h o h ( ) sin( ) =+ + 2 0 ? (2) where: i ( t ) is the instantaneous current i o is the dc component ih is the rms value of current harmonic h and h is the phase angle of the current harmonic.
rev. 0 ad7755 11 using equations 1 and 2, the real power p can be expressed in terms of its fundamental real power ( p 1 ) and harmonic real power ( p h ). ppp h =+ 1 where: pvi 111 1 1 1 1 = = cos C ? (3) and pvhihh hhh h h = = 1 cos C ? (4) as can be seen from equation 4 above, a harmonic real power component is generated for every harmonic, provided that har- monic is present in both the voltage and current waveforms. the power factor calculation has previously been shown to be accurate in the case of a pure sinusoid, therefore the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids. note that the input bandwidth of the analog inputs is 14 khz with a master clock frequency of 3.5795 mhz. analog inputs channel v1 (current channel ) the voltage output from the current transducer is connected to the ad7755 here. channel v1 is a fully differential voltage input. v1p is the positive input with respect to v1n. the maximum peak differential signal on channel 1 should be less than 470 mv (330 mv rms for a pure sinusoidal signal) for specified operation. note that channel 1 has a programmable gain amplifier (pga) with user selectable gain of 1, 2, 8 or 16 (see table i). these gains facilitate easy transducer interfacing. differential input 470mv max peak +470mv agnd v cm v1 v1p v cm 470mv common-mode 100mv max v1n v1 figure 20. maximum signal levels, channel 1, gain = 1 the diagram in figure 20 illustrates the maximum signal levels on v1p and v1n. the maximum differential voltage is 470 mv divided by the gain selection. the differential voltage signal on the inputs must be referenced to a common mode, e.g. agnd. the maximum common mode signal is 100 mv as shown in figure 20. table i. gain selection for channel 1 maximum g1 g0 gain differential signal 001 470 mv 012 235 mv 108 60 mv 1116 30 mv channel v2 (voltage channel ) the output of the line voltage transducer is connected to the ad7755 at this analog input. channel v2 is a fully differential voltage input. the maximum peak differential signal on chan- nel 2 is 660 mv. figure 21 illustrates the maximum signal levels that can be connected to the ad7755 channel 2. differential input 660mv max peak +660mv agnd v cm v2 v2p v cm 660mv common-mode 100mv max v2n v2 figure 21. maximum signal levels, channel 2 channel 2 must be driven from a common-mode voltage, i.e., the differential voltage signal on the input must be referenced to a common mode (usually agnd). the analog inputs of the ad7755 can be driven with common-mode voltages of up to 100 mv with respect to agnd. however best results are achieved using a common mode equal to agnd. typical connection diagrams figure 22 shows a typical connection diagram for channel v1. a ct (current transformer) is the current transducer selected for this example. notice the common-mode voltage for channel 1 is agnd and is derived by center tapping the burden resistor to agnd. this provides the complementary analog input sig- nals for v1p and v1n. the ct turns ratio and burden resistor rb are selected to give a peak differential voltage of 470 mv/ gain at maximum load. v1p agnd 470mv gain rb rf rf ct neutral phase ip v1n cf cf figure 22. typical connection for channel 1
rev. 0 ad7755 12 figure 23 shows two typical connections for channel v2. the first option uses a pt (potential transformer) to provide com- plete isolation from the mains voltage. in the second option the ad7755 is biased around the neutral wire, and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. adjusting the ratio of ra, rb and vr is also a conve- nient way of carrying out a gain calibration on the meter. 660mv ra * rb * vr * v2p agnd rf rf ct neutral phase v2n cf cf 660mv v2p rf neutral phase v2n cf cf * ra >> rf + vr * rb + vr = rf figure 23. typical connections for channel 2 power supply monitor the ad7755 contains an on-chip power supply monitor. the analog supply (av dd ) is continuously monitored by the ad7755. if the supply is less than 4 v 5%, the ad7755 will be reset. this is useful to ensure correct device start-up at power-up and power-down. the power supply monitor has built in hysteresis and filtering. this gives a high degree of immunity to false trig- gering due to noisy supplies. as can be seen from figure 24, the trigger level is nominally set at 4 v. the tolerance on this trigger level is about 5%. the power supply and decoupling for the part should be such that the ripple at av dd does not exceed 5 v 5% as specified for normal operation. av dd 5v 4v 0v internal reset reset time active reset figure 24. on-chip power supply monitor hpf and offset effects figure 25 shows the effect of offsets on the real power calcula- tion. as can be seen, an offset on channel 1 and channel 2 will contribute a dc component after multiplication. since this dc component is extracted by the lpf and used to generate the real power information, the offsets will have contributed a con- stant error to the real power calculation. this problem is easily avoided by enabling the hpf (i.e., pin ac/ dc is set logic high) in channel 1. by removing the offset from at least one channel, no error component can be generated at dc by the multiplica- tion. error terms at cos( t) are removed by the lpf and the digital-to-frequency conversionsee digital-to-frequency conversion section. vtv iti vi vivi ti v t vi t os os os os os os cos cos cos cos cos ? ? () + {} () + {} = ++ () + () + () 2 2 2 v os i os i os v v os i dc component (including error term) is extracted by the lpf for real power calculation 2 frequency rad/s 2 v i 0 figure 25. effect of channel offset on the real power calculation the hpf in channel 1 has an associated phase response that is compensated for on-chip. the phase compensation is activated when the hpf is enabled and is disabled when the hpf is not activated. figures 26 and 27 show the phase error between channels with the compensation network activated. the ad7755 is phase compensated up to 1 khz as shown. this will ensure correct active harmonic power calculation even at low power factors.
rev. 0 ad7755 13 frequency hz 0 100 phase degrees 0.05 0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 200 300 400 500 600 700 800 900 1000 figure 26. phase error between channels (0 hz to 1 khz) frequency hz 40 phase degrees 0.05 0.10 0 0.05 0.10 0.15 0.20 0.25 0.30 45 50 55 60 65 70 figure 27. phase error between channels (40 hz to 70 hz) digital-to-frequency conversion as previously described, the digital output of the low-pass filter after multiplication contains the real power information. how- ever since this lpf is not an ideal brick wall filter implemen- tation, the output signal also contains attenuated components at the line frequency and its harmonics, i.e., cos(h t) where h = 1, 2, 3, . . . etc. the magnitude response of the filter is given by: |()| (/. ) hf fhz = + 1 189 (5) for a line frequency of 50 hz this would give an attenuation of the 2 (100 hz) component of approximately C22 dbs. the dominating harmonic will be at twice the line frequency, i.e., cos (2 t) and this is due to the instantaneous power signal. figure 28 shows the instantaneous real power signal at the output of the cpf which still contains a significant amount of instanta- neous power information, i.e., cos (2 t). this signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time in order to produce an output fre- quency. this accumulation of the signal will suppress or average out any non-dc components in the instantaneous real power signal. the average value of a sinusoidal signal is zero. hence the frequency generated by the ad7755 is proportional to the average real power. figure 28 shows the digital-to-frequency conversion for steady load conditions, i.e., constant voltage and current. 2 v i 2 frequency rad/s lpf digital-to- frequency f1 f2 digital-to- frequency cf instantaneous real power signal (frequency domain) multiplier time frequency f1 frequency fout time v i 0 lpf to extract real power (dc term) cos(2 t) attenuated by lpf figure 28. real power-to-frequency conversion as can be seen in the diagram, the frequency output cf is seen to vary over time, even under steady load conditions. this fre- quency variation is primarily due to the cos (2 t) component in the instantaneous real power signal. the output frequency on cf can be up to 2048 times higher than the frequency on f1 and f2. this higher output frequency is generated by accumu- lating the instantaneous real power signal over a much shorter time while converting it to a frequency. this shorter accumula- tion period means less averaging of the cos (2 t) component. as a consequence, some of this instantaneous power signal passes through the digital-to-frequency conversion. this will not be a problem in the application. where cf is used for calibration purposes, the frequency should be averaged by the frequency counter. this will remove any ripple. if cf is being used to measure energy, e.g., in a microprocessor-based application, the cf output should also be averaged to calculate power. because the outputs f1 and f2 operate at a much lower frequency, a lot more averaging of the instantaneous real power signal is carried out. the result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output.
rev. 0 ad7755 14 interfacing the ad7755 to a microcontroller for energy measurement the easiest way to interface the ad7755 to a microcontroller is to use the cf high frequency output with the output frequency scaling set to 2048 f1, f2. this is done by setting scf = 0 and s0 = s1 = 1, see table iv. with full-scale ac signals on the analog inputs, the output frequency on cf will be approxi- mately 5.5 khz. figure 29 illustrates one scheme which could be used to digitize the output frequency and carry out the neces- sary averaging mentioned in the previous section. time 10% average frequency cf frequency ripple mcu up/ down counter timer cf revp* ad7755 *revp must be used if the meter is bidirectional or direction of energy flow is needed figure 29. interfacing the ad7755 to an mcu as shown, the frequency output cf is connected to an mcu counter or port. this will count the number of pulses in a given integration time which is determined by an mcu internal timer. the average power is proportional to the average frequency is given by: average frequency average al power counter timer == re the energy consumed during an integration period is given by: energy average power time counter time time counter === for the purpose of calibration, this integration time could be 10 to 20 seconds in order to accumulate enough pulses to ensure correct averaging of the frequency. in normal operation the integration time could be reduced to one or two seconds de- pending, for example, on the required undate rate of a display. with shorter integration times on the mcu the amount of energy in each update may still have some small amount of ripple, even under steady load conditions. however, over a minute or more the measured energy will have no ripple. power measurement considerations calculating and displaying power information will always have some associated ripple that will depend on the integration pe- riod used in the mcu to determine average power and also the load. for example, at light loads the output frequency may be 10 hz. with an integration period of two seconds, only about 20 pulses will be counted. the possibility of missing one pulse always exists as the ad7755 output frequency is running asyn- chronously to the mcu timer. this would result in a one-in- twenty or 5% error in the power measurement. transfer function frequency outputs f1 and f2 the ad7755 calculates the product of two voltage signals (on channel 1 and channel 2) and then low-pass filters this product to extract real power information. this real power information is then converted to a frequency. the frequency information is output on f1 and f2 in the form of active low pulses. the pulse rate at these outputs is relatively low, e.g., 0.34 hz maximum for ac signals with s0 = s1 = 0see table iii. this means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. the result is an output frequency that is proportional to the average real power. the averaging of the real power signal is implicit to the digital-to-frequency conversion. the output frequency or pulse rate is related to the input voltage signals by the following equation. freq v v gain f v ref = ? 806 1 2 14 2 . where: freq = output frequency on f1 and f2 (hz) v 1 = differential rms voltage signal on channel 1 (volts) v 2 = differential rms voltage signal on channel 2 (volts) gain = 1, 2, 8 or 16, depending on the pga gain selection made using logic inputs g0 and g1 v ref = the reference voltage (2.5 v 8%) (volts) f 1C4 = one of four possible frequencies selected by using the logic inputs s0 and s1see table ii. table ii. f 1? frequency selection s1 s0 f 1? (hz) xtal/clkin* 0 0 1.7 3.579 mhz/2 21 0 1 3.4 3.579 mhz/2 20 1 0 6.8 3.579 mhz/2 19 1 1 13.6 3.579 mhz/2 18 note *f 1C4 is a binary fraction of the master clock and therefore will vary if the speci- fied clkin frequency is altered.
rev. 0 ad7755 15 example 1 thus if full-scale differential dc voltages of +470 mv and C660 mv are applied to v1 and v2 respectively (470 mv is the maximum differential voltage that can be connected to channel 1 and 660 mv is the maximum differential voltage that can be con- nected to channel 2), the expected output frequency is calcu- lated as follows: gain = 1, g 0 = g 1 = 0 f 1C4 = 1.7 hz, s 0 = s 1 = 0 v1 = +470 mv dc = 0.47 v (rms of dc = dc) v2 = C660 mv dc = 0.66 v (rms of dc = |dc|) v ref = 2.5 v (nominal reference value). note: if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. freq = = 806 047 066 1 17 25 068 2 ... . . . example 2 in this example, with ac voltages of 470 mv peak applied to v1 and 660 mv peak applied to v2, the expected output fre- quency is calculated as follows: gain = 1, g 0 = g 1 = 0 f 1C4 = 1.7 hz, s 0 = s 1 = 0 v1 = rms of 470 mv peak ac = 0.47/ 2 volts v2 = rms of 660 mv peak ac = 0.66/ 2 volts v ref = 2.5 v (nominal reference value). note: if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. freq = = 806 047 066 1 17 2225 034 2 ... . . . as can be seen from these two example calculations, the maxi- mum output frequency for ac inputs is always half of that for dc input signals. table iii shows a complete listing of all maximum output frequencies. table iii. maximum output frequency on f1 and f2 max frequency max frequency s1 s0 for dc inputs (hz) for ac inputs (hz) 0 0 0.68 0.34 0 1 1.36 0.68 1 0 2.72 1.36 1 1 5.44 2.72 frequency output cf the pulse output cf (calibration frequency) is intended for use during calibration. the output pulse rate on cf can be up to 2048 times the pulse rate on f1 and f2. the lower the f 1C4 frequency selected, the higher the cf scaling (except for the high frequency mode scf = 0, s1 = s0 = 1). table iv shows how the two frequencies are related, depending on the states of the logic inputs s0, s1 and scf. because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous real power. as is the case with f1 and f2, the frequency is derived from the output of the low-pass filter after multiplication. however, because the output frequency is high, this real power information is accumulated over a much shorter time. hence less averaging is carried out in the digital-to- frequency conversion. with much less averaging of the real power signal, the cf output is much more responsive to power fluctuationssee signal processing block in figure 18. table iv. maximum output frequency on cf scf s1 s0 f 1? (hz) cf max for ac signals (hz) 1 0 0 1.7 128 f1, f2 = 43.52 0 0 0 1.7 64 f1, f2 = 21.76 1 0 1 3.4 64 f1, f2 = 43.52 0 0 1 3.4 32 f1, f2 = 21.76 1 1 0 6.8 32 f1, f2 = 43.52 0 1 0 6.8 16 f1, f2 = 21.76 1 1 1 13.6 16 f1, f2 = 43.52 0 1 1 13.6 2048 f1, f2 = 5.57 khz selecting a frequency for an energy meter application as shown in table ii, the user can select one of four frequen- cies. this frequency selection determines the maximum fre- quency on f1 and f2. these outputs are intended to be used to drive the energy register (electromechanical or other). since only four different output frequencies can be selected, the avail- able frequency selection has been optimized for a meter con- stant of 100 imp/kwhr with a maximum current of between 10 a and 120 a. table v shows the output frequency for several maximum currents (i max ) with a line voltage of 220 v. in all cases the meter constant is 100 imp/kwhr. table v. f1 and f2 frequency at 100 imp/kwhr i max f1 and f2 (hz) 12.5 a 0.076 25 a 0.153 40 a 0.244 60 a 0.367 80 a 0.489 120 a 0.733 the f 1C4 frequencies allow complete coverage of this range of output frequencies on f1 and f2. when designing an energy meter the nominal design voltage on channel 2 (voltage) should be set to half-scale to allow for calibration of the meter constant. the current channel should also be no more than half-scale when the meter sees maximum load. this will allow over cur- rent signals and signals with high crest factors to be accommo- dated. table vi shows the output frequency on f1 and f2 when both analog inputs are half-scale. the frequencies listed in table vi align very well with those listed in table v for maxi- mum load.
rev. 0 ad7755 16 c3611 2 7/99 printed in u.s.a. table vi. f1 and f2 frequency with half-scale ac inputs frequency on f1 and f2 s1 s0 f 1? ch1 and ch2 half-scale ac inputs 0 0 1.7 0.085 hz 0 1 3.4 0.17 hz 1 0 6.8 0.34 hz 1 1 13.6 0.68 hz when selecting a suitable f 1C4 frequency for a meter design, the frequency output at i max (maximum load) with a meter con- stant of 100 imp/kwhr should be compared with column 4 of table vi. the frequency that is closest in table vi will deter- mine the best choice of frequency (f 1C4 ). for example, if a meter with a maximum current of 25 a is being designed, the out- put frequency on f1 and f2 with a meter constant of 100 imp/ kwhr is 0.153 hz at 25 a and 220 v (from table v). looking at table vi, the closest frequency to 0.153 hz in column four is 0.17 hz. therefore f 2 (3.4 hzsee table ii) is selected for this design. frequency outputs figure 1 shows a timing diagram for the various frequency out- puts. the outputs f1 and f2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechani- cal impulse counter. the f1 and f2 outputs provide two alter- nating low going pulses. the pulsewidth (t 1 ) is set at 275 ms and the time between the falling edges of f1 and f2 (t 3 ) is ap- proximately half the period of f1 (t 2 ). if however the period of f1 and f2 falls below 550 ms (1.81 hz) the pulsewidth of f1 and f2 is set to half of their period. the maximum output fre- quencies for f1 and f2 are shown in table iii. the high frequency cf output is intended to be used for com- munications and calibration purposes. cf produces a 90 ms- wide active high pulse (t 4 ) at a frequency proportional to active power. the cf output frequencies are given in table iv. as in the case of f1 and f2, if the period of cf (t 5 ) falls below 180 ms, the cf pulsewidth is set to half the period. for example, if the cf frequency is 20 hz, the cf pulsewidth is 25 ms. note: when the high frequency mode is selected, (i.e., scf = 0, s1 = s0 = 1) the cf pulsewidth is fixed at 1 s. therefore t 4 will always be 1 s, regardless of output frequency on cf. no load threshold the ad7755 also includes a no load threshold and start-up current feature that will eliminate any creep effects in the meter. the ad7755 is designed to issue a minimum output frequency. any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on f1, f2 or cf. the minimum output frequency is given as 0.0014% of the full-scale output frequency for each of the f 1C4 frequency selectionssee table ii. for example, an energy meter with a meter constant of 100 imp/kwhr on f1, f2 using f 2 (3.4 hz), the maximum output frequency at f1 or f2 would be 0.0014% of 3.4 hz or 4.76 10 C5 hz. this would be 3.05 10 C3 hz at cf (64 f1 hz). in this example the no load threshold would be equivalent to 1.7 w of load or a start-up current of 8 ma at 220 v. comparing this value to the iec1036 specification which states that the meter must start up with a load equal to or less than 0.4% ib. for a 5a (ib) meter 0.4% of ib is eq uiva- lent to 20 ma. 24-lead plastic dip (n-24) 24 1 12 13 pin 1 1.275 (32.30) 1.125 (28.60) 0.280 (7.11) 0.240 (6.10) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.200 (5.05) 0.125 (3.18) 0.150 (3.81) min 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) outline dimensions dimensions shown in inches and (mm). 24 1 13 12 0.328 (8.33) 0.318 (8.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) pin 1 seating plane 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 24-lead shrink small outline package (rs-24)

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